The memory cell array of NAND-type flash memory has multiple memory cells connected in series to form NAND cell units. Each NAND cell unit has select gate transistors arranged on each end, respectively. Through these select gate transistors, connection is made to bit lines and source lines that are connected to the NAND cell units. In addition, control gates of each memory cell in the NAND cell unit are connected to different respective word lines.
For NAND-type flash memory, multiple memory cells are connected in series with a shared source and drain. The select gate transistors and the bit line and source line contacts can be shared by multiple memory cells, so that it is possible to reduce the size of the memory cells. In addition, for NAND-type flash memory, the shapes of the element regions of the word lines and memory cells are formed in a stripe shape pattern, and so it is possible to miniaturize the overall chip dimensions and realize high storage capacity (density).
With the recent progress in miniaturization of the memory cells, the number of the memory cells contained in the memory cell array has been on the rise, and, related to this trend, the circuit area of the peripheral circuit has also increased as more connecting lines are required. The increase in the circuit area of the peripheral circuit leads to an increase in the length of the data bus adopted for data transceiving between the elements of the sense amplifiers, data latches, and other peripheral circuits. Because it takes time to carry out charging/discharging through the data bus, the process for data read or data write becomes slower as a result. Also, the peak current required for charging/discharging with respect to the data bus increases, which is undesirable.